HMT112U7BFR8C-G7 Datasheet, PDF (40/51 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Registered DIMM

Symbol
Precharge Standby Current
Description
I_DD2N
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Pattern Details:
see Table 5.
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address, Bank
I_{DD2NT Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all}
banks closed; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: toggling according to Table 6;
Pattern Details: see Table 6.
I_DDQ2NT Precharge Standby ODT IDDQ Current
(optional) ^{Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current}
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address, Bank
I_DD2P0 Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Precharge Power Down Mode: Slow
Exit^c)
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address, Bank
I_DD2P1
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit^c)
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address, Bank
I_DD2Q
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: stable at 1; Command, Address, Bank
I_{DD3N Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all}
banks open; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Pattern Details: see
Table 5.
Rev. 0.1 / Nov. 2009
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