HMT112U7BFR8C-G7 Datasheet, PDF (15/51 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Registered DIMM

Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
CK,CK#
VDD, VDDQ (DDR3)
VDD, VDDQ (DDR3L)
Tmin = 10ns
tCKSRX
Tmin = 10ns
Tmin = 200us
T = 500us
RESET#
CKE
COMMAND
READ
Tmin = 10ns
tIS
tXPR
tMRD
tMRD
tMRD
tDLLK
tMOD
1)
MRS
MRS
MRS
MRS
ZQCL
tZQinit
1)
VALID
VALID
BA
READ
ODT
READ
RTT
MR2
MR3
MR1
MR0
tIS
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
VALID
tIS
VALID
NOTE 1: From time point “Td” until “Tk” NOP or DES commands must be applied
between MRS and ZQCL commands.
TIME BREAK
DON’T CARE
Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3
Rev. 0.1 / Nov. 2009
15