HMT112U7BFR8C-G7 Datasheet, PDF (16/51 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Registered DIMM

AC & DC Input Measurement Levels
AC and DC Logic Input Levels for Single-Ended Signals
AC and DC Input Levels for Signal-Ended Command and Address Signals
Single Ended AC and DC Input Levels for Command and Address
Symbol
Parameter
DDR3L-800/1066/1333
Min
Max
Unit Notes
VIH.CA(DC90)
VIL.CA(DC90)
VIH.CA(AC160)
VIL.CA(AC160)
VIH.CA(AC135)
VIL.CA(AC135)
V_RefCA(DC)
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC Input logic high
AC input logic low
Reference Voltage for ADD, CMD inputs
Vref + 0.09
VDD
V
1
VSS
Vref - 0.09
V
1
Vref + 0.160
Note2
V
1, 2
Note2
Vref - 0.160
V
1, 2
Vref + 0.135
Note2
V
1, 2
Note2
Vref - 0.135
V
1, 2
0.49 * VDD
0.51 * VDD
V
3, 4
Notes:
1. For input only pins except RESET, Vref = VrefCA (DC).
2. Refer to “Overshoot and Undershoot Specifications” on page 29.
3. The ac peak noise on V_Ref may not allow V_Ref to deviate from V_RefCA(DC) by more than +/-1% VDD (for
reference: approx. +/- 13.5 mV).
4. For reference: approx. VDD/2 +/- 13.5 mV
5. There levels apply for 1.35 volt (see table above) operation only. If the device is operated at 1.5V (table
“Single Ended AC and DC Input Levels for DQ and DM” on page 17), the respective levels in JESD79-3
(VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), etc.) apply. The 1.5V levels (VIH/L.CA(DC100),
VIH/L.CA(AC175), VIH/L.CA(AC150), etc.) do not apply when the device is operated in the 1.35 voltage
range.
Rev. 0.1 / Nov. 2009
16