HMT112U7BFR8C-G7 Datasheet, PDF (17/51 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Registered DIMM

AC and DC Input Levels for Signal-Ended Signals
DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066 as specified in table below.
DDR3 SDRAM will also support corresponding tDS values (Table 41 on page 120 and Table 47on page 145
in “DDR3L Device Operation”) as well as derating tables Table 44 on page 139 in “DDR3L Device Opera-
tion” depending on Vih/Vil AC levels.
Single Ended AC and DC Input Levels for DQ and DM
Symbol
Parameter
DDR3L-800/1066
Min
Max
DDR3L-1333
Min
Max
Unit Notes
VIH.CA(DC90) DC input logic high
VIL.CA(DC90) DC input logic low
VIH.CA(AC160) AC input logic high
VIL.CA(AC160) AC input logic low
VIH.CA(AC135) AC Input logic high
VIL.CA(AC135) AC input logic low
V_RefDQ(DC)
Reference Voltage for DQ,
DM inputs
Vref + 0.09
VSS
Vref + 0.160
Note2
Vref + 0.135
Note2
0.49 * VDD
VDD
Vref - 0.09
Note2
Vref - 0.160
Note2
Vref - 0.135
0.51 * VDD
Vref + 0.09
VSS
-
-
Vref + 0.135
Note2
0.49 * VDD
VDD
Vref - 0.09
-
-
Note2
Vref - 0.135
0.51 * VDD
V1
V
1
V 1, 2,5
V 1, 2,5
V 1, 2,5
V 1, 2,5
V 3, 4
Notes:
1. For input only pins except RESET, Vref = VrefCA (DC).
2. Refer to “Overshoot and Undershoot Specifications” on page 29.
3. The ac peak noise on V_Ref may not allow V_Ref to deviate from V_RefDQ(DC) by more than +/-1% VDD (for
reference: approx. +/- 13.5 mV).
4. For reference: approx. VDD/2 +/- 13.5 mV
5. There levels apply for 1.35 volt (table above) operation only. If the device is operated at 1.5V (See table
above), the respective levels in JESD79-3 (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), etc.)
apply. The 1.5V levels (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), etc.) do not apply when
the device is operated in the 1.35 voltage range.
Rev. 0.1 / Nov. 2009
17