HMT112U7BFR8C-G7 Datasheet, PDF (23/51 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Registered DIMM

Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and
strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the
requirements in table below. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signals to the midlevel between of VDD and VSS
VDD
CK, DQS
V_IX
V_IX
VDD/2
V_IX
Vix Definition
CK, DQS
VSS
Cross point voltage for differential input signals (CK, DQS)
Symbol
Parameter
DDR3L-800, 1066, 1333
Min
Max
Unit Notes
V_IX
Differential Input Cross Point Voltage
relative to VDD/2 for CK, CK
V_IX
Differential Input Cross Point Voltage
relative to VDD/2 for DQS, DQS
-150
-175
-150
150
mV
175
mV 1
150
mV
Notes:
1. Extended range for V_IX is only allowed for clock and if single-ended clock input signals CK and CK are
monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential
slew rate of CK - CK is larger than 3 V/ns.
2. Refer to the table “Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU” on page 32
for VSEL and VSEH standard values.
Rev. 0.1 / Nov. 2009
23