HMT112U7BFR8C-G7 Datasheet, PDF (20/51 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Registered DIMM

Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
Differential AC and DC Input Levels
Symbol
VIHdiff
VILdiff
VIHdiff (ac)
VILdiff (ac)
Notes:
Parameter
Differential input high
Differential input logic low
Differential input high ac
Differential input low ac
DDR3L-800, 1066, 1333
Min
+ 0.180
Note 3
2 x (VIH (ac) - Vref)
Note 3
Max
Note 3
- 0.180
Note 3
2 x (VIL (ac) - Vref)
Unit Notes
V
1
V
1
V
2
V
2
1. Used to define a differential signal slew-rate.
2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL
(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level
applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications” on page 29.
Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS
Slew Rate [V/ns]
> 4.0
4.0
3.0
2.0
1.8
1.6
1.4
1.2
1.0
< 1.0
tDVAC [ps]
@ |VIH/Ldiff (ac)| = 350mV
min
max
75
-
57
-
50
-
38
-
34
-
29
-
22
-
13
-
0
-
0
-
tDVAC [ps]
@ |VIH/Ldiff (ac)| = 300mV
min
max
175
-
170
-
167
-
163
162
-
161
-
159
-
155
-
150
-
150
-
Rev. 0.1 / Nov. 2009
20