HMT112U7BFR8C-G7 Datasheet, PDF (33/51 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Registered DIMM

DDR3L-1333 Speed Bins
For specific Notes See “Speed Bin Table Notes” on page 34.
Speed Bin
CL - nRCD - nRP
Parameter
Symbol
Internal read command
to first data
t_AA
ACT to internal read or
write delay time
t_RCD
PRE command period t_RP
ACT to ACT or REF
command period
t_RC
ACT to PRE command
period
t_RAS
CL = 5
CL = 6
CWL = 5
CWL = 6, 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
CL = 7 CWL = 6 t_CK(AVG)
CWL = 7
CWL = 5
CL = 8 CWL = 6
CWL = 7
CWL = 5, 6
CL = 9
CWL = 7
CWL = 5, 6
CL = 10
CWL = 7
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
Supported CL Settings
Supported CWL Settings
min
13.5
(13.125)⁸
13.5
(13.125)⁸
13.5
(13.125)⁸
49.5
(49.125)⁸
DDR3-1333H
9-9-9
max
20
—
—
—
36
9 * tREFI
2.5
1.875
1.875
1.5
1.5
Reserved
Reserved
3.3
Reserved
Reserved
Reserved
< 2.5
Reserved
Reserved
Reserved
< 2.5
Reserved
Reserved
<1.875
Reserved
<1.875
Reserved
6, 8, (7), 9, (10)
5, 6, 7
Unit
Note
ns
ns
ns
ns
ns
ns
1,2, 3,4, 6
ns
4
ns
1, 2, 3, 6
ns
1, 2, 3, 4, 6
ns
4
ns
4
ns
1, 2, 3, 4, 6
ns
1, 2, 3, 4
ns
4
ns
1, 2, 3, 6
ns
1, 2, 3, 4
ns
4
ns
1, 2, 3, 4
ns
4
ns
1, 2, 3
ns
n_CK
n_CK
Rev. 0.1 / Nov. 2009
33