HMT112U7BFR8C-G7 Datasheet, PDF (38/51 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Registered DIMM

IDD
IDDQ (optional)
VDD
RESET
CK/CK
CKE
CS
RAS, CAS, WE
DDR3L
SDRAM
A, BA
ODT
ZQ
VSS
VDDQ
DQS, DQS ^{RTT = 25 Ohm}
DQ, DM,
VDDQ/2
TDQS, TDQS
VSSQ
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[Note: DIMM level Output test load condition may be different from above]
Application specific
memory channel
environment
IDDQ
Test Load
Channel
IO Power
Simulation
IDDQ
Simulation
IDDQ
Simulation
Correction
Channel IO Power
Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported
by IDDQ Measurement
Rev. 0.1 / Nov. 2009
38