HMT112U7BFR8C-G7 Datasheet, PDF (31/51 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Registered DIMM

Refresh parameters by device density
Refresh parameters by device density
Parameter
RTT_Nom Setting
512Mb 1Gb 2Gb 4Gb
REF command ACT or
REF command time
tRFC
90
110
160
300
Average periodic
refresh interval
tREFI
0 °C ≤ T_CASE ≤ 85 °C
85 °C < T_CASE ≤ 95 °C
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
8Gb Units Notes
350 ns
7.8 us
3.9 us 1
Standard Speed Bins
DDR3L SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3L-800 Speed Bins
For specific Notes See “Speed Bin Table Notes” on page 34.
Speed Bin
CL - nRCD - nRP
Parameter
Internal read command to first data
Symbol
t_AA
DDR3-800E
6-6-6
min
max
15
20
ACT to internal read or write delay time
t_RCD
15
—
PRE command period
t_RP
15
—
ACT to ACT or REF command period
t_RC
52.5
—
ACT to PRE command period
CL = 5
CL = 6
CWL = 5
CWL = 5
Supported CL Settings
Supported CWL Settings
t_RAS
t_CK(AVG)
t_CK(AVG)
37.5
9 * tREFI
Reserved
2.5
3.3
6
5
Unit Notes
ns
ns
ns
ns
ns
ns _{1, 2, 3, 4}
ns
1, 2, 3
n_CK
n_CK
Rev. 0.1 / Nov. 2009
31