GM82C765B Datasheet, PDF (34/36 Pages) Hynix Semiconductor – FLOPPY DISK SUBSYSTEM CONTROLLER

The Read/Write head within the FDD is moved
from cylinder to cylinder under control of the
Seek command. FDC has four independent
Present Cylinder Registers for each drive. They
are cleared only after the Recalibrate command.
The FDC compares the PCN (Present Cylinder
Number) which is the current head position with
the NCN (New Cylinder Number) which is the
current head position with the NCN (New
Cylinder Number), and if there is a difference,
performs the following operations:
PCN<NCN: Direction signal to FDD set to a 1
(high), and step pulses are issued.
(Step In)
PCN>NCN: Direction signal to FDD set to a 0
(low), and step pulses are issued.
(Step Out)
The rate at which step pulses are issued is
controlled by SRT (Stepping Rate Time) in the
Specify command. After each step pulse is issued
NCN is compared against PCN, and NCN=PCN,
the SE (Seek End) flag is set in Status Register 0
to a 1 (high), and the command is terminated. At
this point FDC interrupt goes high. Bits
BOB-D3B in the Main status Register are set
during the seek operation and are cleared by the
sense interrupt status command.
During the command phase of the Seek operation
the FDC is in the FDC busy state: but during the
Execution phase, it is in the non-busy state,
another Seek command may be issued, and in
this manner parallel Seek operations may be done
on up to four drives at once. No other command
can be issued for as long as the FDC is in the
process sending step pulses to any drive
If the time to write three bytes of Seek command
exceeds 150 uS, the timing between the first two
step pulses may be shorter than set in the Specify
command by as much as 1ms.
RECALIBRATE
The function of this command is to retract the
Read/Write head within the FDD to the track 0
position. The FDC clears the contents of the PCN
counter and checks the status of the Track 0
signal from the FDD. As long as the Track 0
GM82C765B
signal is low, the Direction signal remains 0
(Low) and step pulses are issued. When the
Track 0 signal goes high, the SE (Seek End) flag
in Status Register 0 is set to a 1 (high) and the
command is terminated. If the Track 0 signal is
still low after 77 step pulses have been issued for
the GM82C765B,the FDC sets the SE (Seek
End) and EC (Equipment Check) flag of Status
Register 0 to both 1s (highs), and terminates the
command after bits 7 and 6 of Status Register 0
are set to 0 and 1 respectively. The ability to do
overlap Recalibrate commands to multiple FDDs
and the loss of the Ready signal, as described in
the Seek command, also applies to the
Recalibrate command.
Sense Interrupt Status
An interrupt signal is generated by the FDC for
one of the following reasons.
1. Upon entering the Result phase of:
a. Read Data command
b. Read A Track command
c. Read ID command
d. Read Deleted Data command
e. Write Data command
f. Format A Cylinder command
g. Write Deleted Data command
h. Scan commands
2. Ready line of FDD changes state
3. End of Seek or Recalibrate command
4. During Executing phase in the non-DMA
mode
Interrupts caused by reasons 1and 4 above occur
during normal command operations and are
easily discernible by the processor. During and
Executing phase in non-DMA mode. DB5 in the
Main Status Register is high. Upon entering the
Result phase, this bit gets cleared. Reasons 1 and
4 do not require Sense Interrupt Status
commands. The interrupt is cleared by
Reading/Writing data to the FDC. Interrupts
caused +y reasons 2 and 3 above may be
uniquely identified with the aid of the Sense
Interrupt Status command. This command, when
issued, resets the Interrupt signal and via bits 5, 6,
and 7 of Status Register 0 identifies the cause of
the interrupt.
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