GM82C765B Datasheet, PDF (18/36 Pages) Hynix Semiconductor – FLOPPY DISK SUBSYSTEM CONTROLLER

* BASE, SPECIAL, AND PC AT MODES
Base, Special, and PC AT modes allow subtle
differences which the user may find desirable.
The Control Register may be used in any mode
without altering functionality.
* BASE MODE
After a hardware reset, RST active, the
GM82C765B will be held on soft reset, SRST
active, with the normally driven signals, DMA
request and IRQ request outputs tristated. Base
mode may be initiated at this time by a chip
access by the host. Although this may be any
read or write, it is strongly recommended that
the Base mode user’s first chip access be a read
of the Master Status Register. Once Base mode
is entered, the soft reset is released, and IRQ
and DMA are driven. Base mode prohibits the
use of the Operations Register, hence there can
be no qualifying by DMAEN and no soft resets.
The Drive Select outputs, DS1 to DS4 , offer
a 1 of 4 decoding of the Unit Select bits
resident in the command structure.
Pin RWC represents Reduce Write Current
and is indicative of when write
precompensation is necessary.
* SPECIAL MODE
Special mode allows use of the Operations
Register for the DMAEN signal as a qualifier
and to do a software driven device reset,
SRST . To enter Special mode, the Operations
Register is loaded with (1X00X0XX), setting
mode Select to a logic 1 disabling MOEN1 and
MOEN2 and causing SRST to be active.
Then a read of the Control Register address,
LDCR and RD , will set the device into
Special mode. The DS1 through DS4 is
again offered in this mode, as is RWC .
* PC AT Mode
For PC AT compatibility, users will write to
the Operations Register, LDOR and WR ;
this action, performed after a hardware reset,
or in the Base mode, initiates PC AT mode. PC
GM82C765B
AT mode can also be entered from Special
mode by loading the Operations Mode Select
to a logic 0, disabling MOEN1 and MOEN2,
and causing SRST to be active. Then a read
of the Control Register address sets the device
into PC AT mode. The DS outputs are now
replaced with the DSEL and MOEN signals
buffered from the Operations Register.
DMAEN and SRST are supported and
compatible with the current BIOS. RWC
pinfunction is now RPM so that users with
two speed drives may reduce spindle speed per
minute to 300 revolutions per minute when
active low, used to reduce write current when a
slower data rate is selected for a given drive.
Figure 3 illustrates the relationship among the
three modes.
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