GM82C765B Datasheet, PDF (13/36 Pages) Hynix Semiconductor – FLOPPY DISK SUBSYSTEM CONTROLLER

output the data onto the data bus.
If the processor can not handle interrupt fast
enough (every 13uS for the MFM mode and
27uS for the FM mode), then it may poll the
main status Register and bit D7 (RQM) functions
as the Interrupt signal.
If a Write Command is in process then the
WR Signal performs the reset to the Interrupt
signal.
All timings mentioned above double for mini
floppy data rates. Note that in the non-DMA
mode it is necessary to examine the main Status
Register to determine the cause of the interrupt
signs is could be a data interrupt or a command
terminaton interrupt, either normal or abnormal.
If the GM82C765B is in the DMA mode, no
inter-rupt signals are generated during the
Execution phase. This signifies the beginning of
the Result phase. When the first byte of data is
read during the Result phase, the Interrupt is
auto-matically cleared (IRQ=0). It should be
noted that in PC AT usage, non-DMA Host
transfers and not the normal procedure. If the
user chooses to do so, the GM82C765B will
successfully complete commands, but will
always give abnormal termination error status
since TC is qualified by an inactive DACK .
The RD or WR signals should be asserted
while Dack is true. The CS signal is used in
conjunction with RD and WR as a gating
function during programmed I/O operations.
If the non-DAM mode is chosen, the DACK
signal should be pulled up to V_CC . It is important
to note that during the Result phase all bytes
shown in the Command Table must be read. The
Read Data Command for example, has several
bytes of data in the Result phase. All seven bytes
must be read Data command. The GM82C765B
will not accept a new command until all seven
bytes have been read. Other commands may
require fewer bytes to be read during the Result
phase. The GM82C765B contains five Status
Registers. The Main Status Registers (ST0, ST1,
ST2, and ST3) are available only during the
Result phase and may be read only after
completing a command.
The particular command that has been
executed determines how many of the Status
Registers will be read.
The byte of data which are sent to the
GM82C765B
GM82765B to form the command phase, and are
read out of the GM82C765B in the result phase,
must occur in the order shown in the command
Table. The command code must be sent first and
the other bytes sent in the prescribed sequence.
No foreshortening of the command or Result
phase is allowed. After the last byte of data in the
Command phase is sent to the GM83C765B, the
Execution phase of automatically starts. In a
similar fashion, when the last byte of data is read
out in the result phase, the command is
automatically ended and the GM82C765B is
ready for a new command.
CONTROL REGISTER
The Control Register provides support logic that
latches the two LSBs of the data bus upon
receiving LDCR and WR . CS should not be
active when this happens. These bits are used to
select the desired data rate, which in turn controls
the internal clock generation. Clock switchover is
internally “deglitched” allowing continuous
operation after change data rates.
If the Control Register is not used, the data rate is
governed by the supplied clock or crystal. The
frequency must be 64X the desired MFM data
rate, up to a maximum frequency of 16 MHz.
This implies a maximum data rate of 250 kb/S.
unless the Control Register is used. Switching
this clock must be “glitchless” or the device will
need to be reset.
Table 1 presents the Control Register.
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