GM82C765B Datasheet, PDF (19/36 Pages) Hynix Semiconductor – FLOPPY DISK SUBSYSTEM CONTROLLER

READ MASTER
STATUS REG.
BASE
MODE
HARDWARE
RESET
WRITE 80 TO
OPER REG
READ CONT REG
LDCR, RD
WRITE TO
OPER REG.
PC AT
MODE
SPECIAL
MODE
WRITE 00 TO
OPER REG
READ CONT
REG. LDCR, RD
Fig. 3 Flow Diagram Depicting Relationship of Base, Special, and PC AT
modes.
l POLLING ROUTINE
DS1
DS2
DS3
DS4
GM82C765B
After any reset the GM82C765B, (a hard
RST or soft SRST , will automatically go into
a Polling routine. In between commands (and
between step pulse in the SEEK Command),
the GM82C765B polls all four FDDs looking
for a change in the ready line from any of the
drives. Since the drive is always presumed
ready, an interrupt will only be generated
following a reset. This occurs because a reset
forces Not ready status, which then promptly
becomes ready.
Note that in special or PC AT mode if
DMAEN is not valid prior to 1mS after reset
goes inactive, then IRQ may be already set and
pending when finally enabled onto the bus.
The polling of the ready line by the
GM82C765B occurs continuously between
commands. Each drive is polled every
1,024mS, except during the READ/WRITE
commands. For minifloppies, the polling rate is
2,048mS. The drive polling sequence is
1-2-4-3. Please note that in the PC AT mode,
the user will not see the polling at the Drive
Select signals, figure 4 illustrates the Drive
Select Polling time
Fig. 4. Drive select polling timing
* DEVECE RESETS
The GM82C765B supports both hardware reset
(RST) pin (19) and a software reset ( SRST )
through use of the Operations Register. The RST
pin will cause a device reset for the active
duration. RST causes a default to Base mode, and
default selects 250k MFM (or 125k FM, code
dependent) as the data rate (16 MHz input clock).
SRST will reset the microcontroller as did the
RST, but will not affect the value set for the
internal timers-HUT, FTL, and SRT.
If the XTAL oscillators are used, instead of the
TTL driven clock inputs, the hardware RST
active time requirement will bootstrap the circuit
into guaranteed oscillation in a fixed amount of
time.
The extended reset time allows the growth of the
oscillation to produce stable internal clock timing
19