GM82C765B Datasheet, PDF (12/36 Pages) Hynix Semiconductor – FLOPPY DISK SUBSYSTEM CONTROLLER

MAIN
MICROPROCESSOR
INTERFACE
BUS
V_CC =+5V
GM82C765B
40 VCC
1 RD
2. WR
4 A0
16 IRQ
19 RST
WD 27
WE 26
STEP 29
DIRC 28
HDL 35
HS 25
7-14 DB0-DB7
15 DMA
5 DACK
6 TC
DS1 30
DS2 32
DS3 MO1 33
DS4 MO2 34
RWC RPM 36
ADDRESS
RECODE
CKT
CLOCK
CKTS
GND
GND
3 CS
17 LDOR
VCC ^{18 LDCR}
22 DRV
VCC _{24 PCVAL}
23 CLK1
21 CLK2
RDD 20
WP 37
TROO 36
IDX 39
* DCHG 40
VSS 31
GM82C765B
FLOPPY
DISK
DRIVE
150 Ω
150 Ω
150 Ω
150 Ω
150 Ω
INTERFACE
CONNECTOR
* PLCC version of
GM82C765B
Fig 2. TYPICAL GM 82C765B APPLICATION SYSTEM
Inputs, except the data bus, are Schmitt
trig-ger receivers and can be hooked up to a bus
or backplane without any additional buffering.
During the command or result phases, the
main status Register must be ready by the
processor before each byte of information is
written into or read from the data Register. After
each byte of data is read from or written into the
data Register, the CPU should wait for 12uS
before reading the main status Register. Bits D6
and D7 in the main status Register must be in a 0
and 1 state, respectively, before each byte of the
command word may be written into the
GM82C765B. Many of the command require
multiple bytes. As a result, the Main status
Register must be read prior to each byte transfer
to the GM82C765B. During the result phase,
Bits D6 and D7 in the Main status Register must
both be 1’s (D6-1 and D7-1) before reading
each byte from the Data Register. Note that this
regarding of the main status Register before
each byte transfer to the GM82C765B is
re-quired only in the Command and result phases,
and not during the Execution phase. Note also
that DB6 and DB7 in the MSR can be polled
in-stead of waiting 12uS. When they have the
right bit settings, the GM82C765B is ready for
com-mands. This might save some time.
During the Execution phase, the main status
register need not be read. If the GM82C765B
is in the non-DMA Mode, then the receipt of
each data byte is indicated by an interrupt signal
on pin 16 (IRQ-1). The generation of a Read
signal (RD-0) will clear the interrupt as well as
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