GM82C765B Datasheet, PDF (20/36 Pages) Hynix Semiconductor – FLOPPY DISK SUBSYSTEM CONTROLLER

∗ _{DATA SEPARATOR}
The Data Separator is a Digital Phase Lock
Loop Floppy Disk Data Separator (DPLL). It was
designed to address high performance error rates on
floppy disk drives, and to provide superior
performance in terms of available bit jitter tolerance. It
contains the necessary logic to achieve classical 2nd
order, type 2, phase locked loop performance. DPLL is
used as the Data Separator in the GM82C765B system.
Figure 5 illustrates the DPLL implified block diagram.
The bit jitter tolerance for the data separator is 60%,
Which guarantees an error rate of < 10E-9.
∗ _{WRITE PRECOMPENSATION}
The BM82C765B maintains the stand first level
algorithm to determine when write precompensation
should be applied.
The EARLY and LATE signals are used internally to
GM82C765B
select the appropriate delay in the write data pulse
stream.
The encoded WRITE DATA signal is synchronized to
the 16 MHz clock if this is the frequency on CLK1 pin
(23), and clocked through a shift register before a
multiplexer gates the chosen bit to the output.
The output data pulse width has a 25% duty cycle,
i.e., one fourth of the bit cell period, and equal to one
half the WCLK period.
When PCVAL pin (24) = 1, all data will be
precompensated by + 187nS precompensation will be
generated. For frequencies other than 16 MHz on the
CLK1 pin, the precompensation values will be two and
three clock cycles respectively.
When the non-standard data rate using CLK2 is chosen,
the MFM precompensation will always be two clock
cycles.
For 9.6MHz, this is +208nS. In this case, this PCVAL
function is disabled
DSKD
DATA
SYNCHRONIZATION
P
H
A
S
E
DETE-
CTION
TRANSIENT RESPONSE
STATE FILTERING
STEADY STATE
FREQUENCY
FILTERING
RDATA
RESYNCHRONIZATIO
N
SEPD
Phase
SEPCLK
SUMMER
DIGITAL
CONTROLLED
OSCILLATOR
SEPCLK
REFCLK
CLOCK GENERATION
CD1
CD2
SCLK
Fig. 5. DPLL Simplified BLOCK DIAGRAM
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