GM82C765B Datasheet, PDF (14/36 Pages) Hynix Semiconductor – FLOPPY DISK SUBSYSTEM CONTROLLER

GM82C765B
TABLE 1. CONTROL REGISTER
CR1 CR0 DRV
0
0
X
0
0
X
0
1
0
0
1
1
1
0
X
1
0
X
1
1
X
DATA RATE
500K
250K
250K
300K
250K
125K
125K
COMMENTS
MFM
FM
MFM
MFM
MFM, RST Default
FM, RST Default
RPM (In PC AT MODE)
1
1
0
0
1
1
0
MASTER STATUS REGISTER
The Master Status Register is an eight-bit
register that contains the status information of
the FDC, any may be accessed at any time.
Only the Master Status Register may be read
and used to facilitate the transfer of data
between the processor and GM82C765B. The
DIO and RQM bits in the Master Status
Register indicate when data is ready and in
which direction data will be transferred on the
data bus. The maximum time between the last
RD or WR during a Command or Result
phase and DIO and RQM getting set is 12us if
500 kb/S MFM data rate is selected. (If 250
kb/s MFM is selected, the delay is 24uS.) For
this reason, everytime the Master Status
Register is read, the CPU should 12us. The
maximum time from the trailing edge of the
last RD in the result phase to when DB4
(FDC busy) goes low is 12 uS.
TABLE 2. MASTER STATUS REGISTER BITs
BIT
NO.
NAME
DB0 FDD 0 BUSY
DB1 FDD 1 BUSY
DB2 FDD 2 BUSY
DB3 FDD 3 BUSY
DB4 FDC BUSY
DB5 EXECUTION
MODE
DB6 DATA INPUT
DB7 REQUEST FOR
MASTER
SYMBOL
D0B
D1B
D2B
D3B
CB
EXM
DI0
RQM
DESCRIPTION
FDD number 0 is in the Seek Mode. If any of the bits is set,
FDC will not accept READ or WRITE commands.
FDD number 1 is in the Seek Mode. If any of the bits is set,
FDC will not accept READ or WRITE commands.
FDD number 2 is in the Seek Mode. If any of the bits is set,
FDC will not accept READ or WRITE commands.
FDD number 3 is in the Seek Mode. If any of the bits is set,
FDC will not accept READ or WRITE commands.
A READ or READ command is in progress. FDC will not accept
any other commands.
This bit is set only during Execution phase in non-DMA Mode.
When DBS goes low Execution phase has ended and Results phase
has started. It operates only during non-DMA Mode of operation.
Indicates direction of data transfer between FDC and DATA
Register. If DIO=1, then transfer is from DATA Register to the
Processor. If DIO=0, transfer is from Processor to the Data Register.
Indicates Data Register is ready to send or receive data to or from
the Process. Both bits DIO and RQM should be used to perform the
handshaking function of “ready” and “direction” to the Processor.
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