GM82C765B Datasheet, PDF (3/36 Pages) Hynix Semiconductor – FLOPPY DISK SUBSYSTEM CONTROLLER

GM82C765B
PIN
MENMO
DIP PLCC ^-MIC
SIGNAL
NAME
6
6 TC
TERMINAL
COUNT
7-14
7-14
DBO thru
DB7
DATA BUS 0
Thru
DATA BUS 7
15 15 DMA
DIRECT
MEMORY
ACCESS
16 16 IRQ
INTERRUPT
REQUEST
DISK
17 DCHGEN CHANGE
ENABLE
17 18 LDOR
LOAD
OPERATIONS
REGISTER
18 19 LDCR
LOAD
CINTROL
REGISTER
19 20 RST
RESET
20 21 RDD
22 XT2
23 XT2
READ DISK
DATA
XTAL 2
XTAL2
21
CLK2
CLOCK2
(condinued on next page)
I/O
FUNCTION
This signal indicates to GM82C765B that data transfer is
complete. If DMA operational mode is selected for
command execution, TC will be qualified by DACK , but
not in the programmed I/O execution. In PC AT or Special
I
ST
mode, qualification by DACK requires the Operations
mode, qualification by DACK requires the operations
resister signal DMAEN to be logically true. Note also that
in PC AT mode, TC will be qualified by DACK , whether in
DMA or non-DMA host operation. programmed I/O in PC
AT mode will cause an abnormal termination error at the
completion of a command.
I/O
BI
8-Bit bi-directional, tri-state, data bus.
D0 is the least significant bit (LSB).
D7 is the most significant bit (MSB)
DMA request for byte transfer of data.
O In Special or PC AT mode, this pin is tristated, enabled by
BI the DMAEN signal from the Operation Register. This pin is
driven in the Base mode.
Interrupt request indicating the completion of command
O
BI
execution or data transfer requests (in non DMA mode).
Normally driven in base mode. In special or PC AT mode,
this pin is tri-stated, enabled by the DMAEN signal from the
Operations Resister.
I
ST
This input must be at logic = 0 to enable DCHG input
status at pin 40 to be placed on DB7 during a RD = 0 of
LDCR = 0. Internal pull-up.
Address decode which enables the loading of the Operations
I Resister. Internally gated with WR creates the strobe
ST which latches the two LSBS from the data bus into the
Operation Resister.
Address decode which enables the loading of the Control
I Resister. Internally gated with WR creates the strobe
ST which latches the two LSRs from thedata bus into the
Control Resister.
I
ST
Reset controller, placing microsequencer in idle. Resets
device outputs. Puts in base mode, not PC AT or Special
mode.
I
ST
This is the raw serial bit stream from the disk drive. Each
falling edge of the pulses represents a flux transition of the
encoded data.
O XTAL oscillator drive output for 44 pin PLCC should be
N left floating if TTL inputs used at pin 23.
I XTAL oscillator input used for non-standard data rates. It
N may be driven with a TTL level signal
I
N
TTL level clock input used for non-standard data rates is
9.6MHz for 300 kbs, and can only be selected from the
Control Register. * XT2 (PIN23) of 44 pin-PLCC
3