GM82C765B Datasheet, PDF (2/36 Pages) Hynix Semiconductor – FLOPPY DISK SUBSYSTEM CONTROLLER

Pin Configuration
GM82C765B
RD
WR
CS
AO
DACK
TC
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DMA
IRQ
LDOR
LDCR
RST
RDD
1
2
3
4
5
6
7
8
9
10
GM82C765B
11
12
13
14
15
16
17
18
19
20
40
VCC
39
IDX
38
TROO
37
WP
36
RPM, RWC
35
HDL
34
MO2. DS4
33
MO1, DS3
32
DS2
DCHG
WP
31
VSS
TROO
30
DS1
IDX
29
STEP
28
DIRC
VCC
RD
WR
27
WD
CS
26
WE
A0
25
HS
CACK
TC
24
PCVAL
23
CLK1
22
DRV
21
CLK2
39 38 37 36 35 34 33 32 31 30 29
40
28
41
27
42
26
43
25
44
24
1
GM82C765B PL
23
2
22
3
21
4
20
5
19
6
18
7 8 9 10 11 12 13 14 15 16 17
HS
PCVAL
XT1
XT1
DRV
XT2
XT2
RDD
RST
LDCR
LDOR
DBO DB2 DB4 DB6 DMA DCHGEN
DB1 DB3 DB5 DB7 IRQ
1. Pin Descriptions
PIN NO
DIP PLCC
1
1
MNEMOMIC
RD
SIGNAL NAME
READ
2
2
WR
WRITE
3
3
CS
A0
4
4
CHIP SELECT
ADDRESS LINE
DACK
5
5
DMA
ACKNOWLEDG E
(condinued on next page)
I/O
FUNCTION
I Control Signal for transfer of data or status onto the
ST data bus by the GM82C765B
I Control signal for latching data form the bus into the
GM82C765B buffer register.
ST _{Selected when 0 (Low) allowing RD or WR}
operation from the host
I Address line selecting data (=1) or status (=0)
ST information
(A0 = Logic 0 during _WR is illegal)
I Used by the DMA Controller to transfer data from
ST the GM82C765B onto the bus. Logical equivalent to
CS ^{and A0=1. In special or PC AT mode, this}
signal is qualified by DMAEN from the Operation
Register.
2