HD66520 Datasheet, PDF (9/45 Pages) Hitachi Semiconductor – 160-Channel 4-Level Grayscale Display Column Driver with Internal Bit-Map RAM

HD66520T
Address Management Circuit: Converts the addresses input via A15–A0 from the system to the
addresses for a memory map of the on-chip RAM. When several LSIs (HD66520s) are used, only the LSI
whose address space, set by pins LS0, LS1, and SHL, contains the input address, accepts the access from
the system, and enables the inside. The address management circuit enables configuration of the LCD
display system with memory addresses not affected by the connection direction, and reduces burdens of
software and hardware in the system. Refer to the How to Use the LS1 and LS0 Pins to set pins LS0,
LS1, and SHL.
Timing Control Circuit: This circuit controls arbitration between display access and draw access.
Specifically, it controls access timing while receiving signals FLM, CL1, &6, :(, and 2( as input. FLM
and CL1 are used to perform refresh (display access), that is, to transfer line data to the liquid crystal
circuit. &6, :(, and 2( are used for the CPU to perform draw operation (draw access), that is, to read
and write display data from and to the internal RAM. This circuit also generates a timing signal for the
FRC control circuit to implement four-level grayscale display.
Line Counter: Operates refresh functions. When FLM is high, the counter clears the count value and
generates an address to select the first line in the RAM section. The counter increments its value
whenever CL1 is valid and generates an address to select subsequent lines in the RAM section.
Bidirectional Buffer: Controls the transfer direction of the display data according to signals from pins
:( and 2( in draw operation from the system.
Word Line Decoder: Decodes duty addresses (A15 to A7) and selects one of 240 lines in the display
RAM section, and activates one-line memory cells in the display RAM section.
Data Line Decoder: Decodes pin addresses (A6 to A0) and selects a data line in the display RAM
section for the 7-bit memory cells in one-line memory cells activated by the word line decoder.
I/O Selector: Reads and writes 8-bit display data for the memory cells in the RAM section.
Display RAM: 160 × 240 × 2-bit memory cell array. Since the memory is static, display data can be held
without refresh operation during power supply.
FRC Circuit: Implements FRC (frame rate control) function for four-level grayscale display. For details,
refer to Half Tone Display.
Data Latch Circuit (1): Latches 160-pixel grayscale display data processed by the FRC control circuit
after being read from the display RAM section by refresh operation. This circuit is needed to arbitrate
between display access for performing liquid crystal display and draw access from the CPU.
Data Latch Circuit (2): This circuit again outputs the data in data latch circuit (1) synchronously with
signal CL1.
LCD Drive Circuit: Selects one of LCD select/deselect power levels V4R to V1R and V4L to V1L
according to the grayscale display data, AC signal M, and display-off signal . ',632)) The circuit is
configured with 160 circuits each generating LCD voltage to turn on/off the display.
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