HD66520 Datasheet, PDF (30/45 Pages) Hitachi Semiconductor – 160-Channel 4-Level Grayscale Display Column Driver with Internal Bit-Map RAM

HD66520T
Arbitration Control
The HD66520 controls the arbitration between draw access and display access. The draw access reads
and writes display data of the display memory incorporated in the HD66520. The display access outputs
display memory line data to the liquid crystal panel. In this case, draw access is performed before display
access, so continuous access is enabled without having the system to wait. For arbitration control, draw
access is recognized as valid when signal &6 is low.
The following describes the typical examples of display memory access state during arbitration control.
Sequence Line Data Transfer Display Access Performed by Subsequent Line Data Transfer
If no draw access is attempted, normal display access is performed when signal CL1 is low (Figure 28).
Draw Access 1
If draw access is attempted when signal CL1 is high, draw access is performed regardless of the display
access (Figure 29).
CS
CL1
Display memory
access state
nth line data
display access
nth + 1 line data
display access
Figure 28 Sequence Line Data Transfer
CS
CL1
Display memory
access state
Draw access
nth line data
display access
Draw access
nth + 1 line data
display access
Figure 29 Draw Access (1)
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