HD66520 Datasheet, PDF (27/45 Pages) Hitachi Semiconductor – 160-Channel 4-Level Grayscale Display Column Driver with Internal Bit-Map RAM

HD66520T
Display-Data Transfer
Display RAM data is transferred to 160-bit data latch circuits 1 and 2 at each falling edge of the CL1
clock pulse. Since display data transfer and RAM access to draw data are completely synchronous-
separated in the LSI, there will be no draw data loss or display flickering due to display data transfer
timing.
The first line data transfer involves the first line marker (FLM), which initializes a line counter, and
transfers the first line data to data latch circuits 1 and 2. Subsequent line data transfers involve
transferring the second and the subsequent line data to data latch circuits 1 and 2 while incrementing the
line counter value.
First Line Data Transfer
The line counter is initialized synchronously with an FLM signal. The first line is transferred to data latch
circuits 1 and 2 at the falling edge of the CL1 (Figure 22).
Subsequent Line Data Transfer
The second and the subsequent line data are transferred to data latch circuits 1 and 2 at the falling edge of
the CL1 to update the line counter value (Figure 23).
CL1
FLM
Line counter
Data latch circuit 1
Data latch circuit 2
(Y1 to Y160)
X+1
Xth + 1 line
1
1st line
Xth line
2
2nd line
1st line
Figure 22 First Line Data Transfer
CL1
Line counter
n
n+1
Data latch circuit 1
nth line
nth + 1 line
Data latch circuit 2
(Y1 to Y160)
nth – 1 line
nth line
Note: Outputs Y1 to Y160 are converted into four levels before output according the liquid crystal altemating signal.
Figure 23 Subsequent Line Data Transfer
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