HD66520 Datasheet, PDF (6/45 Pages) Hitachi Semiconductor – 160-Channel 4-Level Grayscale Display Column Driver with Internal Bit-Map RAM

HD66520T
Pin Functions
Control Signals
LS0 and LS1 (Input): The LS pins can assign four (0 to 3) ID numbers to four LSIs, thus making it
possible to connect a maximum of four HD66520s sharing the same &6 pin to the same bus (Figure 2.)
SHL (Input): This pin reverses the relationship between LCD drive output pins Y1 to Y160 and
addresses. There is no need to change the address assignment for the display regardless of whether the
HD66520 is mounted from the back or the front of the LCD panel. Refer to Driver Layout and Address
Management for details.
FLM (Input): When the pin is high, it resets the display line counter, returns the display line to the start
line, and synchronizes common signals with frame timing.
CL1 (Input): At each falling edge of data-transfer clock pulses input to this pin, the latch circuits latch
display data and output it to the liquid crystal display driver section.
M (Input): AC voltage needs to be applied to liquid crystals to prevent deterioration due to DC voltage
application. The M pin is a switch signal for liquid crystal drive voltage and determines the AC cycle.
',632)) (Input): A control signal to fix liquid crystal driver output to liquid crystal select high level.
When this pin is low, liquid crystal drive outputs Y1 to Y160 are set to liquid crystal select high level V1.
The display can be turned off by setting the outputs of the common driver to level V1. In this case,
display RAM data will be retained. Therefore, if signal ',632)) returns to high level, liquid crystal
drive outputs will return to normal display state. Draw access can be executed when signal ',632)) is
either in high or low state.
ID = 0
ID = 2
HD66520 HD66520
320
480
LCD panel
HD66520 HD66520
ID = 1
ID = 3
LS1 LS0 ID No.
L
L
0
L
H
1
H
L
2
H
H
3
L: Low level
H: High level
RAM Address Arrangement
Upper-left of LCD panel
Lower-left of LCD panel
Upper-right of LCD panel
Lower-right of LCD panel
Figure 2 LS Pins and Address Assignment
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