HD66520 Datasheet, PDF (7/45 Pages) Hitachi Semiconductor – 160-Channel 4-Level Grayscale Display Column Driver with Internal Bit-Map RAM

HD66520T
Power Supply Pins
V – _{CC1 2} and GND1–2: These pins supply power to the logic circuit.
V – _{CC1 2} and V_EE1–₂: These pins supply power to the liquid crystal circuits.
V1L, V1R, V2L, V2R, V3L, V3R, V4L, V4R: These pins are used to input the level power supply to
drive the liquid crystal.
Bus Interface
&6 (Input): A basic signal of the RAM area. When &6 is low (active), the system can access the on-chip
RAM of the LSI whose address space, set by LS0, LS1, and SHL pins, contains the input address. When
&6 is high, it is prohibited to access the RAM.
In addition, this signal is used for arbitration control when draw access from the CPU competes with
display access that is used to transfer line data to the liquid crystal panel. Note that there are restraints for
the pulse width, as shown in Figure 3. The example shown here is when V_CC = 3V for a write operation.
A0 to A15 (Input): A bus to transfer addresses during RAM access. Upper nine bits (A15 to A7) are
duty-direction addresses, and lower seven bits (A6 to A0) are output pin-direction addresses.
:( (Input): When :( is during low level, the RAM is in active mode, and during high level, it is
prohibited to access the RAM. This is used to write display data to the RAM. Only the LSI whose address
space, set by pins LS0, LS1, and SHL, contains the input address can be written to when &6 is low.
2( (Input): When 2( is during low level the RAM is in active mode, and during high level, it is
prohibited to access the RAM. This is used to read display data from the RAM. Only the LSI whose
address space, set by pins LS0, LS1, and SHL, contains the input address can be read from when &6 is
low.
DB0 to DB7 (Input/Output): The pins function as data input/output pins. They can accommodate to a
data format with 2 bits/pixel, which implement packed-pixel four-level grayscale display.
180 ≤ t_CHW (ns)
180 ≤ t_CLW ≤ t_FS – 1000 (ns)
CS
FLM
CL1
t_CLW
t_FS
t_CHW: CS high-level width
t_CLW: CS low-level width
t_CHW
Note: Refer to restraints for details on pulse-width restraints.
Figure 3 &6(Input)
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