HD66520 Datasheet, PDF (36/45 Pages) Hitachi Semiconductor – 160-Channel 4-Level Grayscale Display Column Driver with Internal Bit-Map RAM

HD66520T
Chip Select Low Level Width
When continuous draw access (burst access) is performed when signal &6 is low, the maximum display
access time, that is, t_FS–1000 (ns) is necessary for the chip select low level width (Figure 35). This is
needed to secure the display access period for the first line.
When common driver HD66503 is used together with the HD66520, t_FS can be calculated with the
following formula.
t_{FS =}
1
4·n_DUTY·f_FLM
f_FLM: frame frequency
n : _DUTY duty
When write operation is performed with the burst access having a frame frequency of 70 Hz and a duty
cycle of 1/240, display data of 77 bytes can be consequtively written in one burst access (write cycle is
180 ns).
CS
FLM
CL1
Display memory
access state
t_CLR (t_CLW)
t_FS
1
Draw access
2
1st line data
display access
2nd line data
display access
2nd line data access
Figure 35 Chip Select Low Level Width
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