HD66520 Datasheet, PDF (32/45 Pages) Hitachi Semiconductor – 160-Channel 4-Level Grayscale Display Column Driver with Internal Bit-Map RAM

HD66520T
Draw Access 3
If draw access is attempted when signal FLM is high, stop the display access is suspended to perform the
draw access (Figure 32). After the draw access, the display access is performed again. As a result, even if
draw access is attempted asynchronously, at least one of the two display accesses will be performed.
Note: In order to satisfy draw access 3 and transfer the first line data, there are restraints for the period
when pins FLM and CL1 are both high and for the low level pulse width of pin &6. Refer to
Restraints for details on the restraints for the pulse width.
CS
Draw access
FLM
CL1
Display memory
access state
Draw access
2nd line data
display access
1st line data
display access
1st line data
display access
Figure 32 Draw Access (3)
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