HD66520 Datasheet, PDF (31/45 Pages) Hitachi Semiconductor – 160-Channel 4-Level Grayscale Display Column Driver with Internal Bit-Map RAM

HD66520T
Draw Access 2
If draw access is attempted when signal CL1 is low, the display access is suspended to perform draw
access (Figure 30). After the draw access, the display access is performed again. As a result, even if draw
access is attempted asynchronously, at least one of the display accesses will be performed.
Display Access by First Line Data Transfer
If no draw access is attempted, display access for the first line is performed when signal FLM is high and
CL1 is low. The display access for the second line is performed when signal CL1 is low (Figure 31).
CS
CL1
Display memory
access state
Draw access
nth line data
display access
Draw access
nth line data
display access
nth + 1 line data
display access
Figure 30 Draw Access (2)
CS
FLM
CL1
Display memory
access state
1st line data
display access
2nd line data
display access
Figure 31 First Line Data Transfer
1044