HD66520 Datasheet, PDF (28/45 Pages) Hitachi Semiconductor – 160-Channel 4-Level Grayscale Display Column Driver with Internal Bit-Map RAM

HD66520T
Draw Access
Random Cycle
Random cycle sequence is the same as that for the general-purpose SRAM interface (Figures 24 and 25).
It can easily be connected to a CPU address bus and data bus.
A15 to 0
CS
OE
WE
DB7 to 0 out
DB7 to 0 in
Valid Dout
Figure 24 Read Cycle
A15 to 0
CS
OE
WE
DB7 to 0 out
DB7 to 0 in
Valid Din
Figure 25 Write Cycle
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