HD66520 Datasheet, PDF (10/45 Pages) Hitachi Semiconductor – 160-Channel 4-Level Grayscale Display Column Driver with Internal Bit-Map RAM

HD66520T
Configuration of Display Data Bit
Packed Pixel Method
For grayscale display, multiple bits are needed for one pixel. In the HD66520, two bits are assigned to
one pixel, enabling a four-level grayscale display.
One address (eight bits) specifies four pixels, and pixel bits 0 and 1 are managed as consecutive bits.
When grayscale display data is manipulated in bit units, one memory access is sufficient, which enables
smooth high-speed data rewriting.
The bit data to input to pin DB7, DB5, DB3, and DB1 becomes MSB and the bit data to input via pin
DB6, DB4, DB2, and DB0 is LSB.
4 pixels/address
Address: n
Address: n + 1
Address: n + 2
Bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 0 1 0 0 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Physical memory
FRC control circuit
0123
0022
1 1 3 3 Grayscale level
LCD display state
Note: Black is shown when the LCD select high-level power supply V1 (M = 1) and LCD select
low-level power V2 (M = 0) are selected. White is shown when the LCD non-select
high-level power supply V3 (M = 1) and LCD non-select low-level power supply V4 (M = 0)
are selected.
Figure 5 Packed Pixel System
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