HD61830 Datasheet, PDF (8/43 Pages) Hitachi Semiconductor – LCDC (LCD Timing Controller)

HD61830/HD61830B
Refresh Address Counters (RAC1/RAC2)
The refresh address counters, RAC1 and RAC2, control the addresses of external RAM, character generator
ROM (CGROM), and extended external ROM. The RAC1 is used for the upper half of the screen and the
RAC2 for the lower half. In the graphic mode, 16-bit data is output and used as the address signal of
external RAM. In the character mode, the high order 4 bits (MA12–MA15) are ignored. The 4 bits of line
address counter are output instead and used as the address of extended ROM.
Character Generator ROM
The character generator ROM has 7360 bits in total and stores 192 types of character data. A character code
(8 bits) from the external RAM and a line code (4 bits) from the line address counter are applied to its
address signals, and it outputs 5-bit dot data.
The character font is 5 × 7 (160 characters) or 5 × 11 (32 characters). The use of extended ROM allows 8 ×
16 (256 characters max.) to be used.
Cursor Address Counter
The cursor address counter is a 16-bit counter that can be preset by instruction. It holds an address when the
data of external RAM is read or written (when display dot data or a character code is read or written). The
value of the cursor address counter is automatically increased by 1 after the display data is read or written
and after the set/clear bit instruction is executed.
Cursor Signal Generator
The cursor can be displayed by instruction in character mode. The cursor is automatically generated on the
display specified by the cursor address and cursor position.
Parallel/Serial Conversion
The parallel data sent from the external RAM, character generator ROM, or extended ROM is converted
into serial data by two parallel/serial conversion circuits and transferred to the liquid crystal driver circuits
for upper screen and lower screen simultaneously.
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