HD61830 Datasheet, PDF (7/43 Pages) Hitachi Semiconductor – LCDC (LCD Timing Controller)

HD61830/HD61830B
Block Functions
Registers
The HD61830/HD61830B has the five types of registers: instruction register (IR), data input register (DIR),
data output register (DOR), dot registers (DR), and mode control register (MCR).
The IR is a 4-bit register that stores the instruction codes for specifying MCR, DR, a start address register,
a cursor address register, and so on. The lower order 4 bits DB0 to DB3 of data buses are written in it.
The DIR is an 8-bit register used to temporarily store the data written into the external RAM, DR, MCR,
and so on.
The DOR is an 8-bit register used to temporarily store the data read from the external RAM. Cursor address
information is written into the cursor address counter (CAC) through the DIR. When the memory read
instruction is set in the IR (latched at the falling edge of E signal), the data of external RAM is read to DOR
by an internal operation. The data is transferred to the MPU by reading the DOR with the next instruction
(the contents of DOR are output to the data bus when E is at the high level).
The DR are registers used to store dot information such as character pitches and the number of vertical
dots, and so on. The information sent from the MPU is written into the DR via the DIR.
The MCR is a 6-bit register used to store the data which specifies states of display such as display on/off
and cursor on/off/blink. The information sent from the MPU is written in it via the DIR.
Busy Flag (BF)
The busy flag = 1 indicates the HD61830 is performing an internal operation. Instructions cannot be
accepted. As shown in Control Instruction, read busy flag, the busy flag is output on DB7 under the
conditions of RS = 1, R/W = 1, and E = 1. Make sure the busy flag is 0 before writing the next instruction.
Dot Counters (DC)
The dot counters are counters that generate liquid crystal display timing according to the contents of DR.
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