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| HD61830 Datasheet, PDF (40/43 Pages) Hitachi Semiconductor – LCDC (LCD Timing Controller) | |||
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HD61830/HD61830B
2. ROM/RAM read timing
T1
CR
a
b
(*1)
tDCE
tHCE
CE
(*2)
2.4V
0.6V
T2
T3
T1
tDCE
tHCE
(*2)
(*1)
a
tDCE
tHCE
OE
0.6V
2.4V
MA0âMA15
0.6V
tDMA
tHMA
Address for upper screen
tSMD
tDMA
tHMA
tDMA
tHMA
Address for
the lower screen
tHMD
tSMD
tHMD
(*3)
tSMD
tHMA
tHMD
2.2V
MD0âMD7
(input)
0.8V
Data for the upper screen
Data for
the lower screen
(*4)
tSRD
tHRD
tSRD
tHRD
RD0âRD7
2.2V
0.8V
Data for the upper screen
Data for the
lower screen
Invalid data
*1 This figures shows the timing for Hp = 8.
For Hp = 7, time shown by âbâ becomes zero. For Hp = 6, time shown by âaâ and âbâ
become zero.
Therefore, the number of clock pulses during T1 become 4, 3, or 2 in the case of Hp = 8,
Hp = 7, or Hp = 6 respectively.
*2 The waveform for instructions with memory read is shown with a dash line. In other cases,
the waveform shown with a solid line is generated.
*3 When an instruction with RAM read/write is executed, the value of cursor address is
output. In other cases, invalid data is output.
*4 When an instruction with RAM read is executed, HD61830B latches the data at this timing.
In other cases, this data is invalid.
3. Test load circuit
VCC
Test point
R
D1 RL
D2
C D3
D4
RL = 2.4 kâ¦
R = 11 kâ¦
C = 50 pF (C includes jig capacitance)
Diodes D1 to D4 : 1S2074 H
40
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