HD61830 Datasheet, PDF (15/43 Pages) Hitachi Semiconductor – LCDC (LCD Timing Controller)

HD61830/HD61830B
10. Clear Bit: (Execution time: 36 µs) The clear/set bit instruction sets 1 bit in a byte of display data RAM
to 0 or 1, respectively. The position of the bit in a byte is specified by N_B and RAM address is specified by
cursor address. After the execution of the instruction, the cursor address is automatically increased by 1. N_B
is a value from 1 to 8. N_B = 1 and N_B = 8 indicates LSB and MSB, respectively.
Register
Instruction reg.
Bit clear reg.
R/W RS
0
1
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
1
0
0
0
0
0
0
(N_B – 1) binary
Set Bit
Register
Instruction reg.
Bit set reg.
R/W RS
0
1
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
1
1
0
0
0
0
0
(N_B – 1) binary
11. Read Busy Flag: (Execution time: 0 µs) When the read mode is set with RS = 1, the busy flag is
output to DB7. The busy flag is set to 1 during the execution of any of the other instructions. After the
execution, it is set to 0. The next instruction can be accepted. No instruction can be accepted when busy
flag = 1. Before executing an instruction or writing data, perform a busy flag check to make sure the busy
flag is 0. When data is written in the register (RS = 1), no busy flag changes. Thus, no busy flag check is
required just after the write operation into the instruction register with RS = 1.
The busy flag can be read without specifying any instruction register.
Register
Busy flag
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
1 1/0
*
15