HD61830 Datasheet, PDF (31/43 Pages) Hitachi Semiconductor – LCDC (LCD Timing Controller)

HD61830/HD61830B
HD61830 External RAM and ROM Interface (V_CC = 5 V ±10%, GND = 0 V, T_a = –20 to +75°C)
Item
Symbol Min
Typ
Max
Unit
SYNC delay time
t _DSY
—
—
SYNC pulse width Low level
t _WSY
900
—
200
ns
—
ns
CPO cycle time
t _CCPO
900
—
—
ns
CPO pulse width
High level
t _WCPOH
450
—
—
ns
Low level
t _WCPOL
450
—
—
ns
MA0 to MA15 refresh delay time
t _DMAR
—
—
200
ns
MA0 to MA15 write address delay time t_DMAW
—
—
200
ns
MD0 to MD7 write data delay time
t _DMDW
—
—
200
ns
MD0 to MD7, RD0 to RD7 setup time
t _SMD
900
—
—
ns
Memory address setup time
t _SMAW
250
—
—
ns
Memory data setup time
WE delay time
WE pulse width (low level)
t _SMDW
250
—
t _DWE
—
—
t _WWE
450
—
—
ns
200
ns
—
ns
SYNC
t_DSY
CPO
MA0–MA15
MD0–MD7
RD0–RD7
1
2
V_CC
t_WSY
t_CCPO
1
2
V_CC
t_WCPOL
t_WCPOH
t_DMAR
2.4 V
0.4 V
t_DMAR
*
2.2 V
0.8 V
t_SMD
2.2 V
0.8 V
*
t_SMD
WE
t_DMAW
*
2.2 V
0.8 V
*
t_DMDW
t_DWE
Notes: 1. No load is applied to all the output terminals.
2. “*” indicates the delay time of RAM and ROM.
t_SMAW
2.4 V
0.4 V
t_SMDW
2.4 V
0.4 V
t_WWE
31