HD61830 Datasheet, PDF (39/43 Pages) Hitachi Semiconductor – LCDC (LCD Timing Controller)

HD61830/HD61830B
HD61830B External RAM and ROM Interface (V_CC = 5V ±10%, GND = 0V, T_a = –20 to +75°C)
Item
Symbol Min
MA0–MA15 delay time
t _DMA
—
MA0–MA15 hold time
t _HMA
40
CE delay time
t _DCE
—
CE hold time
t _HCE
40
OE delay time
t _DOE
—
OE hold time
t _HOE
40
MD output delay time
t _DMD
—
MD output hold time
t _HMDW
10
WE delay time
t _DWE
—
WE clock pulse width
t _WWE
150
MD output high impedance time (1) t_ZMDF
10
MD output high impedance time (2) t_ZMDR
50
RD data set-up time
t _SRD
50
RD data hold time
t _HRD
40
MD data set-up time
t _SMD
50
MD data hold time
t _HMD
40
Notes: 1. RAM write timing
T₁
CR
CE
MA0–MA15
OE
WE
MD0–MD7
(output)
(High impedance)
T1: Memory data refresh timing for upper screen
T2: Memory data refresh timing for lower screen
T3: Memory read/write timing
Typ
Max
Unit
—
300
ns
—
—
ns
—
300
ns
—
—
ns
—
300
ns
—
—
ns
—
150
ns
—
—
ns
—
150
ns
—
—
ns
—
—
ns
—
—
ns
—
—
ns
—
—
ns
—
—
ns
—
—
ns
T₂
T₃
0.7 V_CC
0.3 V_CC
T₁
t_HCE
t_DMA
t_HMA
tt_DHOOEE
t_DWE
t_DWE
0.6V
tt^DHMMAA
2.4V
0.6V
tt_DHOOEE
2.4V
0.6V
t_ZMDR
t_DMD
2.4V
0.6V
2.4V
0.6V
t_WWE
t_ZMDF
Valid
2.4V
data
0.6V
t_HMDW
Notes
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 3
1, 3
1, 3
1, 3
1, 3
1, 3
1, 3
1, 3
2
2
2
2
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