HD61830 Datasheet, PDF (25/43 Pages) Hitachi Semiconductor – LCDC (LCD Timing Controller)

HD61830/HD61830B
HD61830 Electrical Characteristics (V_CC = 5 V ±10%, GND = 0 V, T_a = –20 to
+75°C)
Item
Symbol Min
Typ Max Unit Test Condition Notes
Input high voltage (TTL)
VIH 2.2
—
V_CC
V
1
Input low voltage (TTL)
VIL
0
— 0.8
V
2
Input high voltage
VIHR 3.0
—
V_CC
V
3
Input high voltage (CMOS)
VIHC 0.7 V_CC — V_CC
V
4
Input low voltage (CMOS)
VILC 0
— 0.3 V_CC V
4
Output high voltage (TTL)
VOH 2.4
—
V_CC
V
–I_OH = 0.6 mA 5
Output low voltage (TTL)
VOL 0
— 0.4
V
I_OL = 1.6 mA
5
Output high voltage (CMOS)
VOHC V_CC – 0.4 — V_CC
V
–I_OH = 0.6 mA 6
Output low voltage (CMOS)
VOLC 0
— 0.4
V
I_OL = 0.6 mA
6
Input leakage current
I _IN
–5
—5
µA VIN = 0 – V_CC 7
Three-state leakage current
I _TSL
–10
— 10
µA VOUT = 0 – V_CC 8
Power dissipation (1)
P_W1
—
10 15
mW CR oscillation 9
f_osc = 500 kHz
Power dissipation (2)
P_W2
—
20 30
mW External clock 9
f_cp = 1 MHz
Internal clock operation
(Clock oscillation frequency)
f _osc
400
500 600
kHz C_f = 15 pF ±5% 10
R_f = 39 kΩ ±2%
External clock operation
f _cp
100
500 1100 kHz
11
(External clock operating frequency)
External clock duty
Duty 47.5 50 52.5 %
11
External clock rise time
t _rcp
—
— 0.05 µs
11
External clock fall time
t _fcp
—
— 0.05 µs
11
Pull-up current
I _PL
2
10 20
µA VIN = GND
12
Notes: The I/O terminals have the following configuration:
1. Applied to input terminals and I/O common terminals, except terminals SYNC, CR, and RES.
2. Applied to input terminals and I/O common terminals, except terminals SYNC and CR.
3. Applied to terminal RES.
4. Applied to terminals SYNC and CR.
5. Applied to terminals DB0–DB7, WE, MA0–MA15, and MD0–MD7.
6. Applied to terminals SYNC, CP0, FLM, CL1, CL2, D1, D2, MA, and MB.
7. Applied to input terminals.
8. Applied to I/O common terminals. However, the current which flows into the output drive MOS is
excluded.
25