HD66727 Datasheet, PDF (5/97 Pages) Hitachi Semiconductor – Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver with Key Scan Function

HD66727
LCD-II Family Comparison (cont)
Item
HD66720
HD66717
Power supply voltage
2.7V to 5.5V
2.4V to 5.5V
Liquid crystal drive
voltage
3.0 to 11.0V
3.0 to 13.0V
Maximum display
characters per chip
10 characters ×
1 line/
8 characters ×
2 lines
12 characters ×
1 line/2 lines/3 lines/4 lines
Segment display
42 (extended to 80)
40 (and 10 annunciators)
Display duty ratio
1/9 and 1/17
1/10, 1/18, 1/26, and 1/34
CGROM
9,600 bits
(240 5-×-8 dot
characters)
9,600 bits
(240 5-×-8 dot
characters)
CGRAM
64 bytes
32 bytes
DDRAM
40 bytes
60 bytes
SEGRAM
16 bytes
8 bytes
Segment signals
42
60
Common signals
17
34
Liquid crystal drive
B
B
waveform
Clock source
External resistor
or external clock
External resistor
or external clock
Rf oscillation frequency 160 kHz ± 30%
1-line mode: 40 kHz ± 30%
2-line mode: 80 kHz ± 30%
3-line mode: 120 kHz ± 30%
4-line mode: 160 kHz ± 30%
Liquid crystal voltage
booster circuit
Double or triple
booster circuit
Double or triple
booster circuit
Liquid crystal drive
operational amplifier
None
Built-in for each V1 to V5
Bleeder-resistor for liquid External
crystal drive
Internal 1/4 and 1/6 bias
resistors
Liquid crystal contrast
adjuster
None
Incorporated
Key scan circuit
5 × 6 = 30 keys
None
Extension driver control Independent
signal
control signal
None
Reset function
Internal reset
circuit or reset input
Reset input
Horizontal smooth scroll Dot unit and
line unit
Impossible
Vertical smooth scroll
Impossible
Dot (raster-row) unit
Number of displayed lines 1 or 2
1, 2, 3, or 4
Low power control
Low power mode and sleep Standby mode and
mode
sleep mode
Bus interface
Serial
I²C, serial, 4, or 8 bits
Package
100-pin QFP1420
100-pin TQFP1414
100-pin bare chip
Slim chip with/without bumps
TCP
HD66727
2.4V to 5.5V
3.0 to 13.0V
12 characters ×
1 line/2 lines/3 lines/4 lines
40 (and 12 annunciators)
1/10, 1/18, 1/26, and 1/34
11,520 bits
(240 6-×-8 dot
characters)
32 bytes
60 bytes
8 bytes
60
34
B
External resistor
or external clock
1-line mode: 40 kHz ± 30%
2-line mode: 80 kHz ± 30%
3-line mode: 120 kHz ± 30%
4-line mode: 160 kHz ± 30%
Double or triple
booster circuit
Built-in for each V1 to V5
Internal 1/4 and 1/6 bias
resistors
Incorporated
4 × 8 = 32 keys
None
Reset input
Impossible
Dot (raster-row) unit
1, 2, 3, or 4
Standby mode and
sleep mode
I²C or clock-synchronized serial
Slim chip with/without bumps
TCP
5