HD66727 Datasheet, PDF (16/97 Pages) Hitachi Semiconductor – Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver with Key Scan Function

HD66727
Key Scan Registers (SCAN0 to SCAN7)
The key matrix scanner senses and holds the key states at each rising edge of the key strobe signals that are
output by the HD66727. The key strobe signals are output as time-multiplexed signals from KST0 to
KST7. After passing through the key matrix, these strobe signals are used to sample the key status on four
inputs KIN0 to KIN3, enabling up to 32 keys to be scanned.
The states of inputs KIN0 to KIN3 are sampled by key strobe signal KST0 and latched into register
SCAN0. Similarly, the data sampled by strobe signals KST1 to KST7 is latched into registers SCAN1 to
SCAN7, respectively.
Address Counter (AC)
The address counter (AC) assigns addresses to DDRAM, CGRAM, or SEGRAM. When the address set
instruction is written into the IR, the address information is sent from the IR to the AC. Selection of
DDRAM, CGRAM, and SEGRAM is also determined concurrently by the instruction. Figure 2 shows the
address counter and a sample DDRAM address setting to the address counter.
After writing into (reading from) DDRAM, CGRAM, or SEGRAM, the AC is automatically incremented
by 1 (or decremented by 1).
Address
counter
(AC)
MSB
LSB
AC 6 AC5 AC4 AC3 AC2 AC1 AC0
Example : DDRAM address 4A
1 001 0 1 0
Figure 2 Address Counter and Sample DDRAM Address Setting
Display Data RAM (DDRAM)
Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its capacity is 60 × 8
bits, or 60 characters, which is equivalent to an area of 12 characters × 5 lines. Any number of display lines
(LCD drive duty ratio) from 1 to 4 can be selected by software. Here, assignment of DDRAM addresses is
the same for all display modes (Table 5). The line to be displayed at the top of the display (display-start
line) can also be selected by register settings. See Table 6.
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