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HD66727 Datasheet, PDF (15/97 Pages) Hitachi Semiconductor – Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver with Key Scan Function
HD66727
Block Function Description
System Interface
The HD66727 has two types of system interfaces: I2C bus and clock-synchronized serial. The interface
mode is selected by the IM pin.
The HD66727 has two 8-bit registers: an instruction register (IR) and a data register (DR).
The IR stores instruction codes, such as clear display, return home, and display control, and address
information for display data RAM (DDRAM), character generator RAM (CGRAM), and segment RAM
(SEGRAM). The IR can only be written to by MPU and cannot be read from.
The DR temporarily stores data to be written into DDRAM, CGRAM, SEGRAM, or annunciator. Data
written into the DR from the MPU is automatically written into DDRAM, CGRAM, SEGRAM, or
annunciator by an internal operation. The DR is also used for data storage when reading data from
DDRAM, CGRAM, or SEGRAM. When address information is written into the IR, data is read and then
stored into the DR from DDRAM, CGRAM, or SEGRAM by an internal operation. Data transfer between
the MPU is then completed when the MPU reads the DR. After the read, data in DDRAM, CGRAM, or
SEGRAM at the next address is sent to the DR for the next read from the MPU.
These two registers and the operations can be selected by the register select bit (RS) and the read/write bit
(R/W) as listed in Table 4. For details, see the Serial Data Transfer section.
Table 4 Register Selection by RS and R/W Bits
RS Bit
0
0
1
1
R/W Bit
0
1
0
1
Operation
IR write as an internal operation
Read busy flag (DB7) and key scan data (DB3 to DB0)
DR write as an internal operation (DR to DDRAM, CGRAM, SEGRAM, or
annunciator)
DR read as an internal operation (DDRAM, CGRAM, or SEGRAM to DR)
Busy Flag (BF)
When the busy flag is 1, the HD66727 is in the internal operation mode, and the next instruction will not be
accepted. When RS = 0 and R/W = 1, the busy flag is output from DB7. The next instruction must be
written after ensuring that the busy flag is 0, or data must be transferred in appropriate timing considering
instruction execution times.
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