HD66727 Datasheet, PDF (48/97 Pages) Hitachi Semiconductor – Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver with Key Scan Function

HD66727
a) Basic Data-Receive Timing through the I2C Bus Interface
Transfer start
Transfer end
SCL
(Input)
SDA
(Input/
output)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
MSB
MSB
0 1 1 1 ID1 ID0 RS 0 Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack
Device ID code
RS
R/
W
Slave address
1st byte
Acknowledge
1st instruction
2nd instruction
Acknowledge
Instructions
Acknowledge
b) Basic Data-Transmit Timing through the I2C Bus Interface
Transfer start
Transfer end
SCL
(Input)
SDA
(Input/
output)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
MSB
MSB
0 1 1 1 ID1 ID0 RS 1 Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack
Device ID code RS ^R/
W
Slave address
1st byte
Acknowledge
1st read
Acknowledge
Instructions
2nd read
Acknowledge
c) Consecutive Instruction-Receive Timing through the I2C Bus Interface
SCL
(Input)
SDA
(Input/
output)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
S
1st byte
Start
A
A
A
A
C
Instruction 1
C
Instruction 2
C
Instruction 3
CP
K
K
K
K
Instruction 1
execution time
Instruction 2
execution time
End
Transfers the instruction-2 ACK after instruction 1 has been executed.
d) Consecutive Key-Scanned Data-Transmit Timing through the I2C Bus Interface
SCL
(Input)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
SDA
(Input/ ^S
output)
1st byte
A
A
A
A
C ^{Key-scanned data} C ^{Key-scanned data} C ^{Key-scanned data} C P
K
(SCAN0)
K
(SCAN1)
K
(SCAN2)
K
Start
Transfers the ACK after 8-bit data has been transmitted.
End
e) Consecutive RAM Data-Transmit Timing through the I2C Bus Interface
SCL
(Input)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
SDA
(Input/
output)
S
Start
1st byte
A
A
A
C
RAM data 1
C
RAM data 2
C
K
K
K
RAM data 3
A
CP
K
RAM data 1
RAM data 2
End
execution time
execution time
Transfers the RAM data-2 ACK after the RAM data 1 has been executed.
Figure 23 I²C Bus Interface Timing Sequence
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