HD66727 Datasheet, PDF (49/97 Pages) Hitachi Semiconductor – Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver with Key Scan Function

HD66727
Clock-Synchronized Serial Interface
Setting the IM pin (interface mode pin) to the high level allows standard clock-synchronized serial data
transfer, using the chip select line (CS*), serial data line (SDA), and serial transfer clock line (SCL).
The HD66727 initiates serial data transfer by transferring the start byte at the falling edge of the CS* input.
It ends serial data transfer at the rising edge of the CS* input.
Table 24 illustrates the first bytes of I²C bus interface data and Figure 24 shows the clock-synchronized
serial interface timing sequence.
The HD66727 is selected when the 6-bit chip address in the start byte transferred from the transmitting
device matches the 6-bit device identification code assigned to the HD66727. The HD66727, when
selected, receives the subsequent data string. The least significant bit of the identification code can be
determined by the ID0 pin. The upper five bits must be 01110. Two different chip addresses must be
assigned to a single HD66727 because the seventh bit of the start byte is used as a register select bit (RS):
when RS = 0, an instruction can be issued or key scan data can be read, and when RS = 1, data can be
written to or read from RAM. Read or write is selected according to the eighth bit of the start byte (R/W
bit) as shown in Table 27.
After receiving the start byte, the HD66727 receives or transmits the subsequent data byte-by-byte. Data is
transferred with the MSB first. To transfer data consecutively, adjust the data transfer rate so that the
HD66727 can complete the current instruction before the eighth bit of the next instruction is transferred
(see Table 23, Instruction List). If the next instruction is transferred during execution of the current
instruction, the next instruction will be ignored. Note that the display-clear instruction alone requires longer
execution time than the others.
Table 26 Start Byte of Clock-Synchronized Serial Interface Data
S
Bit 1
Bit 2
Bit 3
Transfer start 0
1
1
Note: Bits 1 to 6 indicate the device ID code.
Bit 4
1
Bit 5
0
Bit 6
ID0
Bit 7
RS
Bit 8
R/W
Table 27 RS and R/W Bit Function of Clock-Synchronized Serial Interface Data
RS R/W Function
0
0
Writes instruction
0
1
Reads key scan data and BF flag
1
0
Writes RAM data
1
1
Reads RAM data
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