HD66727 Datasheet, PDF(22/97 Page) Hitachi Semiconductor – Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver with Key Scan Function

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HD66727 Datasheet, PDF (22/97 Pages) Hitachi Semiconductor – Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver with Key Scan Function

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HD66727

Table 10 Correspondence between Segment Display SEGRAM Addresses (ASEG) and Driver

Signals in the 6-Dot Font Width

ASEG Address

Segment Signals

Common

MSB

LSB D7 D6 D5

Signal

1 0 0 0 * * SEG1, SEG2, SEG3, SEG4, SEG5, SEG6, COMS1

SEG25, SEG26, SEG27, SEG28, SEG29, SEG30,

SEG49 SEG50 SEG51 SEG52 SEG53 SEG54

1 0 0 1 * * SEG7, SEG8, SEG9, SEG10, SEG11, SEG12, COMS1

SEG31, SEG32, SEG33, SEG34, SEG35, SEG36,

SEG55 SEG56 SEG57 SEG58 SEG59 SEG60

1 0 1 0 * * SEG13, SEG14, SEG15, SEG16, SEG17, SEG18, COMS1

SEG37 SEG38 SEG39 SEG40 SEG41 SEG42

1 0 1 1 * * SEG19, SEG20, SEG21, SEG22, SEG23, SEG24, COMS1

SEG43 SEG44 SEG45 SEG46 SEG47 SEG48

1 1 0 0 * * SEG1, SEG2, SEG3, SEG4, SEG5, SEG6, COMS2

SEG25, SEG26, SEG27, SEG28, SEG29, SEG30,

SEG49 SEG50 SEG51 SEG52 SEG53 SEG54

1 1 0 1 * * SEG7, SEG8, SEG9, SEG10, SEG11, SEG12, COMS2

SEG31, SEG32, SEG33, SEG34, SEG35, SEG36,

SEG55 SEG56 SEG57 SEG58 SEG59 SEG60

1 1 1 0 * * SEG13, SEG14, SEG15, SEG16, SEG17, SEG18, COMS2

SEG37 SEG38 SEG39 SEG40 SEG41 SEG42

1 1 1 1 * * SEG19, SEG20, SEG21, SEG22, SEG23, SEG24, COMS2

SEG43 SEG44 SEG45 SEG46 SEG47 SEG48

Notes: 1. When the SFT pin is grounded, the SEG1 pin output is connected to the far left of the LCD

panel, and when the SFT pin is high, the SEG60 pin output is connected to the far left.

2. SEG1 to SEG24 data are identical to SEG25 to SEG48 and SEG49 to SEG60 data.

3. The lower six bits (D5 to D0) of SEGRAM data determine on or off display for each segment. A

segment is selected (turned on) when the corresponding bit is 1, and is deselected (turned off)

when the corresponding bit is 0. The upper two bits (D7 to D6) are invalid.

Timing Generation Circuit

The timing generation circuit generates timing signals for the operation of internal circuits such as

DDRAM, CGROM, CGRAM, and SEGRAM. RAM read timing for display and internal operation timing

by MPU access are generated separately to avoid interfering with each other. Therefore, when writing data

to DDRAM, for example, there will be no undesirable interferences, such as flickering, in areas other than

the display area.

Cursor/Blink Control Circuit

The cursor/blink (or white-black inversion) control is used to produce a cursor or a flashing area on the

display at a position corresponding to the location stored in the address counter (AC).

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