HD66727 Datasheet, PDF (39/97 Pages) Hitachi Semiconductor – Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver with Key Scan Function

Table 20 CGRAM Addresses and Character Codes
Displayed Character
1st character
2nd character
3rd character
4th character
CGRAM Address
“00”H to “07”H
“08”H to “0F”H
“10”H to “17”H
“18”H to “1F”H
HD66727
Character Codes
“00”H
“01”H
“02”H
“03”H
DDRAM Address Set
The DDRAM address set instruction (Figure 20) includes the A (ADD), IRE, and KF bits.
AAAAAAA: Used for setting the DDRAM address into the address counter (AC). The DDRAM addresses
range from “00”H to “4B”H (60 addresses) (Table 21).
Once the DDRAM address is set, data in the DDRAM can be accessed consecutively since the address
counter is automatically incremented or decremented according to the I/D bit setting after each access.
Here, invalid addresses are automatically skipped. The DDRAM address cannot be set during the sleep or
standby mode.
RS R/W DB7
DB0
0 0 1 1 0 IRE KF1 KF0 A A _{Upper bits}
0 0 1 1 1 A A A A A Lower bits
Figure 20 DDRAM Address Set Instruction
Table 21 DDRAM Addresses and Invalid Addresses
Displayed Line
1st line
2nd line
3rd line
4th line
5th line
DDRAM Address
“00”H to “0B”H
“10”H to “1B”H
“20”H to “2B”H
“30”H to “3B”H
“40”H to “4B”H
Invalid Addresses
“0C”H to “0F”H
“1C”H to “1F”H
“2C”H to “2F”H
“3C”H to “3F”H
“4C”H and subsequent addresses
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