MC68HC705C8A_13 Datasheet, PDF (91/222 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
Capture/Compare Timer
Timer Operation
Addr.
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
Register Name
Bit 7
6
5
4
3
2
Timer Control Register ^Read: _ICIE
OCIE
TOIE
0
0
0
(TCR) Write:
See page 94. _{Reset: 0}
0
0
0
0
0
Timer Status Register ^{Read: ICF}
OCF
TOF
0
0
0
(TSR) Write:
See page 96. _{Reset: U}
U
U
0
0
0
Input Capture Register ^Read:
High (ICRH) Write:
See page 100. _Reset:
Bit 15
Bit 14
Bit 13
Bit 12 Bit 11 Bit 10
Unaffected by reset
Input Capture Register ^{Read: Bit 7 Bit 6}
Bit 5
Bit 4
Bit 3
Bit 2
Low (ICRL) Write:
See page 100. _Reset:
Unaffected by reset
Output Compare Register Read:
High (OCRH)
See page 101.
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12 Bit 11 Bit 10
Unaffected by reset
Output Compare Register ^Read: _{Bit 7}
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Low (OCRL) Write:
See page 101. _Reset:
Unaffected by reset
Timer Register High ^Read:
(TRH) Write:
See page 97. _Reset:
Bit 15
Bit 14
Bit 13 Bit 12 Bit 11 Bit 10
Reset initializes TRH to $FF
Timer Register Low ^{Read: Bit 7 Bit 6}
(TRL) Write:
See page 97. _Reset:
Bit 5
Bit 4
Bit 3
Bit 2
Reset initializes TRL to $FC
Alternate Timer Register ^Read:
High (ATRH) Write:
See page 99. _Reset:
Bit 15
Bit 14
Bit 13 Bit 12 Bit 11 Bit 10
Reset initializes ATRH to $FF
Alternate Timer Register ^{Read: Bit 7 Bit 6}
Low (ATRL) Write:
See page 99. _Reset:
Bit 5
Bit 4
Bit 3
Bit 2
Reset initializes ATRL to $FC
= Unimplemented U = Unaffected
1
IEDG
U
0
0
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 0
OLVL
0
0
0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Figure 8-2. Timer I/O Register Summary
MC68HC705C8A — Rev. 3
MOTOROLA
Capture/Compare Timer
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Technical Data