MC68HC705C8A_13 Datasheet, PDF (41/222 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
Memory
Bootloader ROM
Addr.
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: ICF OCF TOF
0
0
0
0
0
Timer Status Register
(TSR) Write:
See page 96.
Reset: U
U
U
0
0
0
0
0
Read: Bit 15 Bit 14 Bit 13 Bit 12
Input Capture Register
Bit 11
Bit 10 Bit 9 Bit 8
High (ICRH) Write:
See page 100.
Reset:
Unaffected by reset
Read: Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2 Bit 1 Bit 0
Input Capture Register
Low (ICRL) Write:
See page 100.
Reset:
Unaffected by reset
Output Compare Register ^Read:
High (OCRH)
See page 101.
Write:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10 Bit 9 Bit 8
Reset:
Unaffected by reset
Read:
Output Compare Register
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2 Bit 1 Bit 0
Low (OCRL) Write:
See page 101.
Reset:
Unaffected by reset
Read: Bit 15 Bit 14 Bit 13 Bit 12
Timer Register High
Bit 11
Bit 10 Bit 9 Bit 8
(TRH) Write:
See page 97.
Reset:
Reset initializes TRH to $FF
Read: Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2 Bit 1 Bit 0
Timer Register Low
(TRL) Write:
See page 97.
Reset:
Reset initializes TRL to $FC
Read: Bit 15 Bit 14 Bit 13 Bit 12
Alternate Timer Register
Bit 11
Bit 10 Bit 9 Bit 8
High (ATRH) Write:
See page 99.
Reset:
Reset initializes ATRH to $FF
Read: Bit 7 Bit 6
Alternate Timer Register
Low (ATRL) Write:
See page 99.
Reset:
Bit 5
Bit 4
Bit 3
Bit 2
Reset initializes ATRL to $FC
Bit 1 Bit 0
= Unimplemented U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 3 of 4)
MC68HC705C8A — Rev. 3
MOTOROLA
Memory
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Go to: www.freescale.com
Technical Data