MC68HC705C8A_13 Datasheet, PDF (82/222 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
Parallel Input/Output (I/O)
7.4.2 Data Direction Register B
The contents of data direction register B (DDRB) shown in Figure 7-5
determine whether each port B pin is an input or an output. Writing a
logic 1 to a DDRB bit enables the output buffer for the associated port B
pin; a logic 0 disables the output buffer. A reset clears all DDRB bits,
configuring all port B pins as inputs. If the pullup devices are enabled by
mask option, setting a DDRB bit to a logic 1 turns off the pullup device
for that pin.
Address: $0005
Bit 7
6
5
4
3
2
1
Read:
DDRB7
Write:
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
Reset: 0
0
0
0
0
0
0
Figure 7-5. Data Direction Register B (DDRB)
Bit 0
DDRB0
0
DDRB7–DDRB0 — Port B Data Direction Bits
These read/write bits control port B data direction. Reset clears bits
DDRB7–DDRB0.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE: Avoid glitches on port B pins by writing to the port B data register before
changing DDRB bits from logic 0 to logic 1.
Technical Data
82
Parallel Input/Output (I/O)
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MC68HC705C8A — Rev. 3