MC68HC705C8A_13 Datasheet, PDF (206/222 Pages) Freescale Semiconductor, Inc – Technical Data

MC68HSC705C8A
Freescale Semiconductor, Inc.
Diagram
Number⁽¹⁾
Characteristic⁽²⁾
Symbol
Min
Max
Unit
Data hold time (outputs)
11
Master (after capture edge)
Slave (after enable edge)
t_HO(M)
t_HO(S)
0.25
0
—
t_CYC(M)
—
ns
Rise time⁽⁷⁾
12
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
t_RM
—
50
ns
t_RS
—
2.0
µs
Fall time⁽⁸⁾
13
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
t_FM
—
50
ns
t_FS
—
2.0
µs
1. Diagram numbers refer to dimensions in Figure 13-8. SPI Master Timing and Figure 13-9. SPI Slave Timing.
2. V_DD = 5 V ± 10%; V_SS = 0 Vdc, T_A = T_L to T_H, unless otherwise noted
3. Signal production depends on software.
4. Time to data active from high-impedance state
5. Hold time to high-impedance state
6. With 200 pF on all SPI pins.
7. 20% of V_DD to 70% of V_DD; C_L = 200 pF
8. 70% of V_DD to 20% of V_DD; C_L = 200 pF
Technical Data
206
MC68HSC705C8A
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MC68HC705C8A — Rev. 3