MC68HC705C8A_13 Datasheet, PDF (55/222 Pages) Freescale Semiconductor, Inc – Technical Data

Freescale Semiconductor, Inc.
Interrupts
Interrupt Sources
4.3.4 Capture/Compare Timer Interrupts
Setting the I bit in the CCR disables all interrupts except for SWI.
4.3.5 SCI Interrupts
The serial communications interface (SCI) can generate these
interrupts:
• Transmit data register empty interrupt
• Transmission complete interrupt
• Receive data register full interrupt
• Receiver overrun interrupt
• Receiver input idle interrupt
Setting the I bit in the CCR disables all SCI interrupts.
• SCI Transmit Data Register Empty Interrupt — The transmit
data register empty bit (TDRE) indicates that the SCI data register
is ready to receive a byte for transmission. TDRE becomes set
when data in the SCI data register transfers to the transmit shift
register. TDRE generates an interrupt request if the transmit
interrupt enable bit (TIE) is set also.
• SCI Transmission Complete Interrupt — The transmission
complete bit (TC) indicates the completion of an SCI transmission.
TC becomes set when the TDRE bit becomes set and no data,
preamble, or break character is being transmitted. TC generates
an interrupt request if the transmission complete interrupt enable
bit (TCIE) is set also.
• SCI Receive Data Register Full Interrupt — The receive data
register full bit (RDRF) indicates that a byte is ready to be read in
the SCI data register. RDRF becomes set when the data in the
receive shift register transfers to the SCI data register. RDRF
generates an interrupt request if the receive interrupt enable bit
(RIE) is set also.
MC68HC705C8A — Rev. 3
MOTOROLA
Interrupts
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Technical Data