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MC68HC705C8A_13 Datasheet, PDF (202/222 Pages) Freescale Semiconductor, Inc – Technical Data
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MC68HSC705C8A
Freescale Semiconductor, Inc.
CM1:CM0
00
01
10
11
Table A-1. Programmable COP Timeout Period Selection
COP
Timeout
Rate
fOP ÷ 215
fOP ÷ 217
fOP ÷ 219
fOP ÷ ÷221
fOSC = 8.0 MHz
fOP = 4.0 MHz
8.192 ms
32.77 ms
131.07 ms
524.29 ms
Programmable COP Timeout Period
fOSC = 4.0 MHz
fOP = 2.0 MHz
fOSC = 3.5795 MHz
fOP = 1.7897 MHz
16.38 ms
18.31 ms
65.54 ms
73.24 ms
262.14 ms
292.95 ms
1.048 s
1.172 s
fOSC = 2.0 MHz
fOP = 1.0 MHz
32.77 ms
131.07 ms
524.29 ms
2.097 s
A.3 5.0-Volt High-Speed DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output high voltage
ILoad = –0.8 mA
PA7–PA0, PB7–PB0, PC6–PC0, TCMP
ILoad = –1.6 mA
PD4–PD1
ILoad = –5.0 mA
PC7
—
VOH
VDD – 0.8
—
—
—
V
—
—
Output low voltage
ILoad = 1.6 mA
PA7–PA0, PB7–PB0, PC6–PC0, PD4–PD1
VOL
—
ILoad = 20 mA
PC7
—
—
0.4
V
—
0.4
Supply current(3)
Run(4)
Wait(5)
Stop(6)
25°C
–40°C to +85°C
—
5.92
14
mA
IDD
—
2.27
7.0
mA
—
5
50
µA
—
2.0
50
µA
1. VDD = 5 V ± 10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range at 25°C.
3. IDD measured with port B pullup devices disabled.
4. Run (operating) IDD measured using external square wave clock source (fOSC = 8.0 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 50 pF on all outputs. CL = 20 pF on OSC2. OSC2 capacitance linearly affects run IDD.
5. Wait IDD measured using external square wave clock source (fOSC = 8.0 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 50 pF on all outputs. CL = 20 pF on OSC2. VIL = 0.2 V, VIH = VDD – 0.2 V. All ports configured as inputs. SPI and SCI
disabled. If SPI and SCI enabled, add 10% current draw. OSC2 capacitance linearly affects wait IDD.
6. Stop IDD measured with OSC1 = VDD. All ports configured as inputs. VIL = 0.2 V, VIH = VDD – 0.2 V.
Technical Data
202
MC68HSC705C8A
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MC68HC705C8A — Rev. 3
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