K20P144M120SF3_1210 Datasheet, PDF (73/86 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

Peripheral operating requirements and behaviors
Table 52. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num.
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
Characteristic
I2S_MCLK cycle time
I2S_MCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
Min.
62.5
45%
250
45%
—
0
—
-1.6
45
0
Max.
—
55%
—
55%
45
—
45
—
—
—
Unit
ns
MCLK period
ns
BCLK period
ns
ns
ns
ns
ns
ns
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
S1
S2
S2
S3
S4
S4
S5
S9
S7
S9
S10
S7
S8
S6
S10
S8
Figure 36. I2S/SAI timing — master modes
Table 53. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num.
S11
S12
Characteristic
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
Min.
1.71
250
45%
Max.
3.6
—
55%
Unit
V
ns
MCLK period
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4, 10/2012.
Freescale Semiconductor, Inc.
73