K20P144M120SF3_1210 Datasheet, PDF (42/86 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

Peripheral operating requirements and behaviors
NFC_CEn
NFC_WE
NFC_IOn
tCS
tWC
tWP tWH
tDS tDH
data
data
tCH
data
Figure 14. Write data latch cycle timing
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
tRC
tRP tREH
tIS
data
data
tRR
tCH
data
Figure 15. Read data latch cycle timing in non-fast mode
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
tRC
tRP tREH
tIS
data
data
tRR
tCH
data
Figure 16. Read data latch cycle timing in fast mode
6.4.4 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
K20 Sub-Family Data Sheet, Rev. 4, 10/2012.
42
Freescale Semiconductor, Inc.